1. Technical Field
The embodiments described herein relate to a semiconductor device and, more particularly, to a semiconductor integrated circuit (IC) device and a method of processing address and command signals thereof.
2. Related Art
In general, one common performance indicator of a semiconductor IC device, such as a graphic memory or a main memory, is power consumption or operational speed. In active operational mode and read/write operational mode, a semiconductor IC device simultaneously processes command and address signal during high-speed operations.
FIG. 1 is a waveform diagram demonstrating a conventional method of using address and command signals in a semiconductor IC device. In FIG. 1, a semiconductor IC device receives address and command signals in a memory controller, such as a Graphic Processing Unit (GPU), together at one time. Here, both the address and command signals received at one time are decoded, and an internal command and an internal address are processed by considering a predetermined timing delay time, such as write latency WL, a burst length BL, and the like.
For example, in a case where a command signal input from an exterior of the IC device is a write command, an internal write command signal ‘icas_WT’ and an internal address signal ‘iADD’ are created to be suitable for a rising edge of a clock pulse signal ‘CLK’, as shown in FIG. 1. In addition, a column selection signal ‘Yi’ is created by combining the internal write command signal ‘icas_WT’ and the internal address signal ‘iADD’.
FIG. 2 is a waveform diagram demonstrating conventional address and command signal processing errors. However, in such a method, since the command signal and the address signal do not have sufficient margins, operation errors are created. That is, the delay of the internal address signal ‘iADD’ occurs due to variation in the Process/Voltage/Temperature (PVT) amounts, as shown in FIG. 2. Accordingly, since the internal write command signal ‘icas_WT’ is superimposed with a different internal address signal ‘iADD’, signal generation errors occur, i.e., an error of the column selection signal ‘Yi’, thereby resulting in operational errors of the semiconductor IC device.